Keysight Eggplant Find by Description reduces script volume by 92%

1 min read     Updated on 08 Jul 2026, 11:49 PM
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AI Summary

Keysight Technologies announced Keysight Eggplant Find by Description, a feature allowing automation engineers to locate interface elements by description rather than screenshots. This reduces script volume by 92% and cuts task time from over an hour to under 15 minutes. The solution addresses the barrier of script upkeep during application changes.

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Keysight Technologies announced Keysight Eggplant Find by Description, a feature allowing automation engineers to locate interface elements by description rather than capturing and matching screenshots. Each test targets an element by its description rather than its visual appearance, enabling it to keep running through redesigns, theme changes, and resolution shifts. This removes the manual recapture work that has historically wasted engineering resources.

Half of organizations believe a chief test automation barrier is the upkeep of scripts that fail as applications change. Maintaining image-based scripts is a hidden cost, as they break when the interface shifts, even when the underlying software runs correctly. Engineers then spend hours recapturing screenshots for cases that should still pass, a cycle that repeats across every release and environment.

With Keysight Eggplant Find by Description, part of Eggplant Studio and Eggplant Functional, an engineer can describe an element, such as a ticket price for a given date, and the software locates it without reference to screenshots, document object model access, or changes to the system under test. In a Keysight demonstration, this reduced script volume by 92 percent and cut the task from over an hour to under 15 minutes. This extends Keysight Eggplant's use of AI and computer vision in test automation, which lets a description keep working as the design changes and applies across legacy desktop, embedded, and web applications.

Key Benefits

Benefit Description
Tests that survive change Descriptions hold up through redesigns, theme updates, and resolution shifts, so automation no longer breaks whenever the interface changes.
Less time on authoring maintenance tests Hours spent writing scripts and fixing broken tests can now be used to expand coverage.
Manual tasks automated When image matching was the only option, testing was manual; now tests can run automatically using text descriptions.

Gareth Smith, Software Quality Engineering General Manager, Keysight, said: "Our goal is to help teams automate more of their testing. However, for too long, the maintenance burden has held that back. Keysight Eggplant Find by Description clears one of the biggest barriers, moving us toward a future where teams automate what they want, not only what their tools allow."

How will competitors in the test automation market respond to Keysight's AI-driven approach?

What impact will this reduction in maintenance time have on software development lifecycles?

Could this technology be extended to automate testing beyond UI elements?

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Keysight and WIN Semiconductors cut GaN MMIC design risk

2 min read     Updated on 30 Jun 2026, 11:19 PM
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Reviewed by
Ashish TScanX News Team
AI Summary

Keysight Technologies and WIN Semiconductors have launched a joint MMIC design workflow to reduce fabrication risk for GaN components in 5G and defense sectors. The integrated solution automates simulation and verification to ensure first pass tapeout success, targeting a projected $2.77 billion GaN RF device market by 2031.

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Keysight Technologies and WIN Semiconductors have introduced a joint Monolithic Microwave Integrated Circuit (MMIC) design workflow to reduce fabrication risk for Gallium Nitride (GaN) components used in 5G, satellite, and defense applications. The new workflow connects on-chip multi-domain simulation, 3D layout with verifications, and off-chip MMIC evaluation board design into a single environment. This integration aims to help design houses achieve first pass tapeout success, avoiding the weeks lost to a foundry respin following a failed tapeout.

The workflow automates the full set of simulation, optimization, and verification steps required to sign off on an MMIC design. By ensuring no analysis is skipped before submission to the foundry, the solution addresses a critical bottleneck where customers often delay purchase commitments until performance can be measured on a physical evaluation board. Engineers can now design and optimize on-chip and off-chip components together, ensuring performance meets specifications verified with test equipment.

Market Context and Strategic Importance

With the global GaN RF device market projected to reach $2.77 billion by 2031, the ability to prove performance on an evaluation board is crucial for securing market share. The workflow supports the growing number of companies developing GaN MMICs for 5G base stations, Wi-Fi access points, satellite payloads, and defense radar systems.

Technical Integration

WIN Semiconductors’ latest NP 120P GaN Process Design Kit (PDK) provides MMIC designers with access to process models and layout rules. These models are integrated within Keysight Advanced Design System (ADS) and RF Circuit Simulation Professional to automate the workflow.

Component Function
WIN NP 120P GaN PDK Provides process models and layout rules
Keysight Advanced Design System (ADS) Platform for on-chip multi-domain simulation
RF Circuit Simulation Professional Automates simulation and verification steps

Richard Kuo, Director of Design Service at WIN Semiconductors, stated that the collaboration delivers a customized Layout Versus Schematic (LVS) solution within the WIN ADS PDK. He emphasized that combining Keysight's ADS expertise with WIN's robust PDK and advanced process technology provides a comprehensive verification solution that streamlines the customer design flow.

Nilesh Kamdar, General Manager of EDA and Design Engineering Software at Keysight, noted that WIN's complete PDK combined with Keysight's simulation and verification tools gives designers a single path from chip design through evaluation board. This allows design houses to prove full system performance before fabrication, giving customers the confidence to commit.

How will this joint workflow impact the time-to-market for new 5G and satellite communication products?

Will this partnership pressure other EDA vendors and foundries to develop similar integrated verification solutions?

Could this workflow reduce the overall cost of GaN component development enough to accelerate adoption in commercial sectors?

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