IBM debuts world's first sub-1 nanometer chip technology
IBM has unveiled a sub-1 nanometer chip technology at the 0.7 nm node, utilizing a new 3D nanostack architecture to pack nearly 100 billion transistors. The technology offers up to 50% more performance or 70% greater energy efficiency compared to 2 nm chips, with a path to production in the next 5 years.

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IBM has introduced the world's first sub-1 nanometer (nm) chip technology at the 0.7 nm node, featuring a revolutionary three-dimensional nanostack transistor architecture. The technology packs nearly 100 billion transistors onto a fingernail-sized chip, nearly twice the density of IBM's 2 nm chip unveiled in 2021. This advancement offers up to 50% more performance or 70% greater energy efficiency than IBM's 2 nm node chips, addressing the physical limits of traditional chip scaling and supporting high-bandwidth data demands for advanced AI workloads.
Nanostack Architecture and Performance
The new transistor architecture, called "nanostack," is the industry's first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors using 3D sequential integration to increase density. The design allows for different material combinations within each stacked layer, optimizing performance and power efficiency independently.
IBM's nanostack architecture was validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability, and functional CMOS inverter operation. Research presented at VLSI 2026 indicates the architecture provides 40% scaling in SRAM, supporting high-bandwidth data demands for advanced AI workloads.
Roadmap and Production Timeline
IBM's semiconductor roadmap projects at least a decade of future scaling with the nanostack architecture. The technology extends logic technology below the 1 nm node, advancing angstrom-level scaling where dimensions approach atomic sizes. IBM expects the earliest adoption of nanostack technology at the sub-1 nm node, with a path to production in as early as the next 5 years.
Research and Development Context
IBM and its partners conduct this work at a semiconductor research facility in Albany, New York. The facility will soon house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool developed by ASML, essential for future logic scaling. Partners including Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd. are collaborating on new High NA EUV processes and tools.
IBM also announced plans to form Anderon, a standalone pure-play quantum foundry, leveraging its quantum computing and semiconductor expertise. This initiative aims to position the United States to manufacture most of the world's quantum wafers.
How will the integration of ASML's High NA EUV lithography tool at the Albany facility impact the timeline and yield for mass-producing 0.7 nm chips?
What are the potential thermal management challenges associated with vertically stacking nearly 100 billion transistors on a fingernail-sized chip?
How might competitors like TSMC and Samsung respond to IBM's nanostack architecture in their own sub-1 nm roadmaps?
































