Spel Semiconductor has secured board approval for a strategic tripartite Memorandum of Understanding (MOU) with California Software Company Limited (Calsoft) and Natronix-India. The decision was finalized during the company’s 205th Board Meeting held on July 29, 2026, marking a significant step in its collaboration efforts within the semiconductor and artificial intelligence sectors. This agreement establishes a clear division of responsibilities, with Spel Semiconductor handling assembly, test, mark, and package operations, while Natronix-India takes charge of semiconductor IC design and design intellectual property.

The board meeting, which commenced at 11:00 am and concluded at 4:15 pm at the company’s registered office, also authorized P. Balamurugan, Head Operations & Whole-Time Director, to negotiate, finalize, and execute the MOU on behalf of the company. The collaboration aims to foster joint research, development, design, and intellectual property creation focused on semiconductor chips, AI, and related advanced technology solutions.

Strategic Collaboration Details

The tripartite agreement brings together three key entities to leverage their respective strengths in the technology value chain. The specific roles assigned under the MOU are detailed below:

Regulatory Compliance and Disclosure

The outcome of the board meeting was disclosed pursuant to Regulation 30 and other applicable provisions of the SEBI (Listing Obligations and Disclosure Requirements) Regulations, 2015. The intimation was submitted to BSE Limited, referencing the earlier notice dated July 27, 2026, which had scheduled the meeting to consider this strategic development.

What the Numbers Show

While financial figures are not disclosed in this procedural filing, the structural division of labor highlights a strategic move towards vertical integration capabilities. By partnering with Natronix-India for IP and design and Calsoft for broader R&D support, Spel Semiconductor is positioning its existing packaging and testing infrastructure within a more comprehensive semiconductor development ecosystem. This alignment suggests a focus on capturing higher value-add activities in the chip manufacturing process beyond traditional OSAT (Outsourced Semiconductor Assembly and Test) services.

Spel Semiconductor Limited’s Board has approved a comprehensive plan to raise up to ₹1,000 crore through domestic and overseas channels to finance the modernization and expansion of its semiconductor manufacturing facilities. The fund-raising initiative aims to bolster investments in manufacturing infrastructure, advanced packaging, testing, automation, and utilities. This strategic expansion is intended to position the company to leverage various government incentive schemes, including the India Semiconductor Mission and Production Linked Incentive (PLI) Schemes.

The Board sanctioned raising funds of up to ₹500 crore via one or more Rights Issues or through a Qualified Institutional Placement (QIP) of equity shares and other eligible securities. Separately, the company approved raising another ₹500 crore through overseas instruments such as Foreign Direct Investment (FDI) and Foreign Currency Convertible Bonds (FCCBs), subject to applicable regulatory approvals.

To facilitate these capital infusion plans, the Board approved increasing the authorised share capital from ₹60 crore to ₹150 crore, subject to shareholder approval. This move necessitates an alteration of Clause V of the Memorandum of Association. Furthermore, the Board resolved to seek shareholder approval under Section 180(1)(c) of the Companies Act, 2013 to enhance the company's borrowing limits up to ₹500 crore.

A Fund Raising Committee comprising directors and key managerial personnel was constituted to oversee the implementation of these initiatives. The committee is authorized to appoint intermediaries and complete necessary regulatory formalities. The Board meeting, held on July 20, 2026, at the company's registered office, commenced at 10:15 A.M. and concluded at 7:45 P.M.

Key Approvals