SK hynix, Sandisk unveil HBF spec with 512GB capacity for AI
SK hynix and Sandisk unveiled the first High Bandwidth Flash (HBF) standard through the Open Compute Project, featuring up to 512GB capacity and scalable bandwidth up to 3.0TB/s. The specification, developed in six months, utilizes UCIe interconnects and supports various NAND stack configurations to enhance AI inference efficiency. SK hynix also showcased its V10 375-layer 4D NAND at FMS 2026, highlighting a 2.5x improvement in power efficiency.

*this image is generated using AI for illustrative purposes only.
SK hynix Inc. and Sandisk Corporation have released the first technical specification for High Bandwidth Flash (HBF) through the Open Compute Project (OCP), establishing a foundational open standard for AI inference memory. Announced on August 3, 2026, the specification defines a new memory layer between High Bandwidth Memory (HBM) and solid-state drives, offering capacities up to 512GB and bandwidths scaling from approximately 0.4TB/s to 3.0TB/s across three performance grades. This development addresses critical bandwidth and capacity scalability challenges in large language models by leveraging NAND technology to deliver high-speed data transfer similar to HBM while significantly expanding storage density.
The standardization effort, completed in just six months since the consortium's launch in February, positions HBF as an interoperable industry solution rather than a proprietary technology. The specification includes system interface standards, electrical guidelines, reliability guidance for HBF die stacks, and software input/output instructions. Crucially, it adopts UCIe (Universal Chiplet Interconnect Express), an open standard interface, allowing flexible integration of HBF technology with various processors, including GPUs and CPUs. This interoperability aims to reduce total cost of ownership and improve token economics for hyperscale data centers optimizing inference workloads.
Technical Specifications
The newly released framework provides detailed parameters for system designers building next-generation AI compute architectures. Key specifications include support for two stack configurations (8-high and 16-high NAND dies) and scalable performance tiers designed to meet diverse workload requirements.
| Specification Component | Detail |
|---|---|
| Capacity | Up to 512GB |
| Bandwidth Grades | Grade 1–3 (approx. 0.4TB/s to 3.0TB/s) |
| Stack Configurations | 8-high and 16-high NAND dies |
| Interconnect Standard | UCIe (Universal Chiplet Interconnect Express) |
| Interface Guidelines | System, electrical, and software I/O |
Google and Tenstorrent joined the consortium as members, contributing to technology validation and ecosystem expansion. The open nature of the OCP framework allows system integrators to design around a standardized HBF interface, potentially lowering barriers to entry compared to bespoke vendor-specific implementations.
Industry Events and Product Roadmap
Coinciding with the specification release, SK hynix is presenting its 'Tiered Memory' solutions at the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California, from August 4 to 6. On August 4, Executive Vice President Kim Chun-sung and Vice President Kang Uk-song will deliver a keynote on orchestrating efficient AI infrastructure through tiered memory architectures. A panel discussion on August 6 will feature representatives from SK hynix, Sandisk, and Google DeepMind, focusing on breaking the memory wall with HBF technology.
Additionally, SK hynix unveiled its tenth-generation (V10) 375-layer 4D NAND wafer at the event. This next-generation product offers a 2.5 times improvement in performance per watt compared to the previous generation, targeting high-efficiency AI infrastructure environments. Mass production of enterprise SSDs based on this architecture is planned for early next year.
What the Numbers Show
The rapid six-month timeline from consortium launch to specification release signals an accelerated pace of standardization in the AI infrastructure sector. By defining clear capacity limits (512GB) and bandwidth tiers (up to 3.0TB/s), the standard provides system architects with predictable performance metrics for designing tiered memory systems. The adoption of the UCIe interconnect standard suggests a strategic shift toward modular, heterogeneous computing designs, where memory and storage components can be optimized independently yet integrated seamlessly. This standardization likely influences future capital expenditure decisions by reducing dependency on single-vendor ecosystems and promoting broader adoption of NAND-based high-bandwidth solutions in inference-heavy workloads.
How will the adoption of the UCIe interconnect standard in HBF impact the competitive landscape between proprietary memory solutions and open-standard modular chiplet architectures?
What specific cost-per-token reductions are hyperscale data centers expected to achieve by integrating HBF into their inference workloads compared to current HBM-only configurations?
Could the standardization of HBF accelerate the transition of large language model training workloads from GPU-centric memory hierarchies to more distributed, tiered storage architectures?

































