India Targets 50% of Global Chip Design Work with Ambitious Semiconductor Roadmap
Minister Ashwini Vaishnaw announced India's ambitious semiconductor roadmap at Davos, targeting 50% of global chip design work and 3nm chip production by 2032. The Semicon 2.0 programme includes Design Linked Incentive 2.0, focusing on six core domains: compute systems, RF, cyber-secure networking, power management, sensors and memory. India has transformed from global scepticism in 2022 to strong international confidence, with Deep Tech Awards launching in November 2026.
*this image is generated using AI for illustrative purposes only.
Union IT and Electronics Minister Ashwini Vaishnaw has announced an ambitious roadmap to position India as a global semiconductor powerhouse, declaring that 50% of the world's semiconductor design work will eventually be carried out from India. Speaking at the World Economic Forum in Davos, the minister outlined comprehensive plans to strengthen India's semiconductor ecosystem through advanced manufacturing capabilities and strategic incentive programmes.
Transformation from Scepticism to Global Confidence
Vaishnaw highlighted India's remarkable transformation in the global semiconductor landscape over recent years. Recalling his first visit to Davos in 2022, he noted that India's semiconductor plans were initially viewed with doubt by the international community. "That scepticism has now turned into optimism," he stated, emphasising that several global leaders have expressed concerns about missing opportunities as India expands its semiconductor ecosystem.
The minister reported strong satisfaction from industrial leaders during a semiconductor roundtable held in Davos, indicating growing international confidence in India's semiconductor programme.
Semicon 2.0 Programme and Advanced Manufacturing Goals
The minister announced that Design Linked Incentive (DLI) 2.0 is currently under development and will be implemented as part of the broader Semicon 2.0 programme. This initiative aims to develop advanced manufacturing capabilities with a specific target of producing 3-nanometre chips domestically by 2032.
| Programme Component: | Details |
|---|---|
| Initiative: | Design Linked Incentive (DLI) 2.0 |
| Parent Programme: | Semicon 2.0 |
| Manufacturing Target: | 3-nanometre chip production |
| Target Timeline: | By 2032 |
| Global Design Share Goal: | 50% of world's semiconductor design work |
Six Core Design Domains Strategy
Vaishnaw outlined six fundamental domains that will form the foundation of India's semiconductor design strategy. These strategic areas are designed to enable India to develop chips for diverse applications across multiple industries:
- Compute systems and microcontrollers
- Radio frequency (RF) technologies
- Cyber-secure networking solutions
- Power management systems
- Advanced sensors
- Memory technologies
The minister explained that gaining strength in these areas will allow India to design chips for a wide range of products, including drones, automobiles and space technologies.
IT Industry Transformation and Deep Tech Recognition
Beyond semiconductors, Vaishnaw projected a major shift in India's IT sector, stating that "the entire IT industry is going to be the largest AI services provider to the world." This transformation aligns with India's broader technology advancement goals.
The minister also announced the launch of Deep Tech Awards to recognise start-ups working in advanced technology areas such as semiconductors and space. The inaugural edition of these awards is scheduled for November 2026, providing a platform to celebrate innovation in critical technology sectors.
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